module cont1s_beh(clk, data_in, start, count, done);
input        clk;
input  [7:0] data_in;
input        start;
output [3:0] count;
output       done;

reg       done;

reg [7:0] data;
reg [2:0] iterat;
reg [3:0] count_int;

always @(posedge clk)
if (start) begin
   iterat = 0;
   done = 0;
   count_int = 0;
   data = data_in;
   repeat (8) begin
      @(posedge clk);
      if (data[iterat])
         count_int = count_int + 1;
      iterat = iterat + 1;
   end
   done = 1'b1; 
end    

assign count = count_int;

endmodule
   
